Clemson Reconfigurable Computing

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Reconfigurable Data Cache

Applications running on hardware often need to access huge amounts of data from an offchip memory. These accesses being offchip, have large latency which is exacerbated by the read/write scheduling delays in the hardware. There is also a growing difference between processor and memory speeds. With reconfigurable hardware we can try to use and application specific approach to lessen the effect of memory latency and speed on processor throughput.

The data cache project is an effort at building a cache that can minimize offchip memory accesses. This is achieved by analyzing memory accesses at the pseudo-code level of the application and designing a suitable prefetch machine and storage.







Please mail Comments/Suggestions to Ranjesh or Srinivas at { jranjes , sbeerav } at parl.clemson.edu