1.  Parity Generation & Detection

In this part of the lab, we will design and build circuits to generate and detect parity in 3-bit words to be transmitted and received on our computer. We will use odd parity. Our parity generator circuit will take 3 input bits , x, y, and z, and produce 1 output bit, P. The truth table is shown below:

How many 2 input AND and OR gates and how many inverters would be required to implement the equation you got for P? (Remember, it takes two 2 input gates to make one 3 input gate)

AND:

  OR:

  NOT:

  This circuit can be implemented with the chips in your lab kit, but that would leave only 1OR gate and no AND gates to implement our entire parity detection circuit !(not to mention that it would be a pain to wire up!). So, how can we simplify this further? This is one of those examples where you see why engineers can't be replaced by computers (yet - but we're working on it). The K-map guarantees us M.S.O.P. form, but that's not the simplest form for this problem. Neither is the M.P.O.S. form we'd get from grouping the zeroes. This K-map shows a checkerboard pattern (every other square), meaning it implements either an XOR or XNOR function. If you look at the equation you got for P, if you did it right it can be rewritten as:

P = (x'y'+xy)z' + (x'y+xy')z

  = (x Åy)'z' + (x Åy)z

If we let A = x Åy then,

P = A'z' + Az = (A Åz)', or

P = (x Åy Åz)'

 
Try that derivation for yourself.

Therefore, we can implement P with a 3-variable XNOR gate. Of course, we don't have a 3 input XNOR gate in oour lab kits, but you can easily build one from 2 XOR gates from a 7486 and 1 inverter (HINT: XOR is associative, like AND or OR, so( x Åy) Åz=x Åy Åz). Use Digital Works to create a macro of your parity generation circuit, and wire it up on your breadboard.

Next, we need to implement a Parity Detector circuit, which will have 4 inputs, x,y,z, and P, and 1 output, E (error), which will be 1 whenever there is a parity error. Fill in the value for E in the truth table for this circuit below. Remember, E will be 1 whenever P is not the correct odd parity bit for the values of x,y, and z:

  Once again, you'll notice that this equation would be a nuisance to wire up, but once again, we see the familiar checkerboard pattern. If we look back at our truth table, you'll notice that E is 1 whenever there is an even number of 1's in the 4 input variables (just like P was 1 whenever there was an even number of 1 's in the input in the table for our generator circuit). Once again, we can implement this function as an XNOR of the four input variables,

E = x Åy Åz ÅP

  Because of this property, XNOR is also known as the even function, and XOR is also known as the odd function (If we changed our truth table so that our output was 1 whenever there was an odd number of 1s, the resulting function would be an XOR; the K-map would still look like a checkerboard, but the first one would be in square 0001 instead of 0000).

Create your parity detection circuit using the equation for E above as a macro in Digital Works with 4 inputs and 1 output, and wire it up on your breadboard (this will require 3 more XOR gates and one more inverter - you should have 2 7486 chips). Hook your parity generator to your parity detector and verify that it works correctly both in lab and in simulation. To test your simulation, embed your generator and detector macros in the same circuit as shown in the figure below:

and hooking it to a switch instead.

2.  Code Conversion

Note: You can leave the circuit from section 1 on your breadboard and wire this one simultaneously...

In this section of the lab, we will use K-maps to design a simple circuit to convert between two different encoding schemes. We will assume that we have two modules from two different manufacturers that need to communicate using two different 3 bit codes, and we have been tasked with designing the circuitry to interface them. The truth table for the conversion is shown below:

  B=__________________________

  C=__________________________

  This gives us three fairly straightforward MSOP equations, each of which won't be too bad to wire up.

However, when I count up the gates, I get 3 AND and 1 OR gate required for A,4 AND and 2 OR gates required for B, and 2 AND and 1 OR gates required for C (Hint: make sure your equations match the gate counts). You might notice that's a total of 9 AND gates, and you only have 8 in your lab kit (2 7408 chips)!

Once again, this requires an engineer to reformulate the equations in a way that we can implement with the parts we have. Certainly we have enough parts to implement A and B with just AND and OR gates, so let's just take a look at C (have to give you the answer here):

C = y'z + xy

We need to reformulate this equation to use something other than AND gates or OR gates. We've already used our XOR gates in part 1 of the lab, so what's left in our kits? There are a couple of 7400 chips left: Quad NAND gates. So, how can we implement the function above with just Nands? We'll learn a more systematic way to do this later in lecture, but for now, let me just replace the two AND operations and one OR operation in the equation for C with NAND operations. Remember, x NAND y = (xy)'

C= ((y'z)'(xy)')'
Using DeMorgan's Theorem, we can simplify C to:

C= ((y'z)'(xy)')' = (y'z)''+(xy)'' = y'z +xy, which is our original equation for C!

 
This means we can implement C as shown below, without changing the function at all: