Design with Unused States

Create a State Table:

PSInNS
ABCxABC
0000000
0001001
0010010
0011011
0100100
0101000
0110010
0111100
1000100
1001000
1010XXX
1011XXX
1100XXX
1101XXX
1110XXX
1111XXX

To Implement with DFF, do three 4 -variable K-maps for A, B, and C:


Next, you may need to check if you're circuit is self-correcting. There is always the possibility that the circuit will get into one of the unused states, perhaps at powerup or in the event of a timing glitch. A self-correcting circuit will then proceed back from the unused state to one of the legal ones. Checking for this can be accomplished by examining the FF input functions created to see what the next state will be, then constructing a new state diagram.

Let's rewrite the last 6 lines of our state table, replacing the don't cares with the actual next states produced by our state equations:

A(t+1)=Da= BC'x'+BCx+Ax'

Db = B'C + Cx'

Dc = A'B'x

ABCxA(t+1)B(t+1)C(t+1)
1010110
1011010
1100100
1101000
1110110
1111100

Now, we'll construct a new (complete) state diagram


Within 1 or 2 clock cycles, this circuit will always resume normal operation, regardless of the input value. It is possible that if the circuit got into states 5 or 7, it would then go to state 6, but from state 6 we must then enter a valid state. Had state 6 gone back to 5 or 7, or if any state had an arrow that looped back on itself, it would have been possible for the circuit to remain in an illegal state indefinitely.

When using edge-triggered flip-flops, there are a number of timing issues which must be considered. Among the most significant are setup and hold time. Setup time is the amount of time you require the inputs of your circuit to remain constant before an edge on which you will trigger. Hold time is the amount of time after an edge used for triggering that the inputsmust continue to remain constant, as indicated in the diagram below:


This is a result of the propagation delay through the edge triggering mechanism. To put it

simply, after a change in inputs, you must wait for the signal to propagate through the

edge-triggering part of the circuit to the SR latch before you can correctly trigger. Once

the clock changes, the clock signal must propagate through the triggering portion to the

latch before you can guarantee that the circuit will not react to an input change.


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